About Me |
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Mr. Prabhat Kumar Patnaik, an Assistant Professor and Head of the Electronics and Communication Engineering Department at Centurion University of Technology and Management, embodies dedication to academic excellence. With affiliations to esteemed organizations such as IEEE and IAENG, alongside prestigious Life Memberships in ISTE and ISRD, Mr. Patnaik showcases a profound commitment to advancing knowledge and innovation. His research focuses on Antennas, Microwave, and Digital Circuits, resulting in numerous publications in renowned international journals and presentations at influential conferences. As the Single Point of Contact for the Swayam/NPTEL local chapter, he cultivates a vibrant learning environment. Moreover, Mr. Patnaik serves as the IEEE Student Branch Counselor and Advisor to the IEEE Antennas and Propagation Society (AP-S) Student Branch Chapter, guiding and inspiring future technologists. |
- RF MEMS
- Digital Design
- Analog Communication Techniques
- Soft Computing and Intelligent Systems
- Digital Electronics Circuit
- Signals and Systems
- Communication Engineering
- Introduction to Digital Signal Processing
- Digital Communication Techniques
- Analog Electronics Circuits
- Embedded Systems
- Communication Systems
- Digital Design
- Digital Circuits
- Antenna and Soft Computing
Research Fields
I have published 15 research articles in various conferences and journal.
Currently I am working in the area of Digital Circuit design, Antenna and Soft Computing Applications.
Recent Publications (International Journals)
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Academic Honors & Awards
Fast Extraction of Resonant Frequency of Square Ring Microstrip antenna using Neural Network Approach
This paper presents an efficient approach based on neural network to design a square ring micro strip antenna. Traditional techniques used to design a square ring antenna are based on EM field simulations like IE3D which is highly CPU intensive and requires lot of time for simulation. Neural networks can be used to map the complex relationship between physical and electrical parameters of ring antenna in an efficient manner. The model once developed can be used with minimal CPU resources and enables fast extraction of output parameter such as resonant frequency. The typical resonant frequency values are first obtained through IE3D and then from samples obtained from IE3D are used to train the neural network .The results obtained by the use of neural networks have been proved to be faster than comparison with IE3D software.
Digital Combinational circuit optimization using Invasive Weed Optimization
Minimization of digital circuits is required to reduce the area, power consumption, propagation delay and number of active gates. Human methods of minimization like Karnaugh map, Quine’ McCluskey, Sasao methods are tedious and are limited to systems with four or five inputs. A new bio-inspired algorithm called Invasive weed optimization (IWO) is used to minimize the combinational circuits. Results are presented to show that IWO based optimization of digital circuits are equivalent to or even with better solution than human design techniques
GSM Based Temperature and Humidity Measurement of SILO
Agriculture plays vital role of any nation’s economy and it depends upon the agricultural growth which leads toward the economic prosperity. India is primarily an agricultural country where large percentage of the population depends upon the farming and the storage of grains plays a crucial part in national economy. The seasonality production of grain and its storage are given priority. So, nowadays silos are extensively used in agriculture for grain storage. In the process of storage of grain, temperature and humidity are the major environmental factors which can influence the grain quality. So, it is necessary to monitor and measure the important parameters continuously during grain storage and the status has to be communicated to the manager in real-time which is more challenging. The traditional methods are just limited to simple manual temperature and humidity testing which are not reliable hence there is a need for smart grain management system with automation which can also avoid hidden security risks. The real-time monitoring of the grain storage system is designed based on Arduino and using GSM module which improves the level of grain storage and reduces the grain losses during storage procedure and reduces manpower and labor intensity.
Controller Design for Bridgeless SEPIC PFC Rectifier Operating in Continuous Conduction Mode
A fairly regulated output voltage can be obtained with a low power factor corrector circuit. When the line voltage is a sinusoidal line voltage, the converter must draw a current which is sinusoidal. To achieve it, a suitable reference sinusoidal signal is generally needed and the control objective is to force the input current to match with the reference current. In the earlier proposed work of the single switch, SEPIC PFC rectifier [1] does not use any controller.
Thus, feedback control is usually used with the converter circuit to achieve regulated output voltage, input current, i.e., input current waveform can be shaped typically by means of pulse width modulation (PWM). Basically, feedback controls are used for regulating the output voltage of the converter and for shaping of input current waveform which distorted due to injection of harmonics and nonlinear loads. This paper reviews different control techniques used for PFC. The paper focuses on design and analysis of controller for the PFC rectifier using average current mode controller.
Parameter Analysis and Different Geometrical Approach for Ultra Wideband Planar Antenna
In this context, two major part is clearly explained .One is parameter analysis in time domain
for wireless application and for different UWB architecture .Other one is different geometrical approach
to design Ultra wideband (UWB) for different band width, resonant frequency, patterns multiple notch.
In Parameter analysis, all types of antennas (double ridged TEM, resonant monopole, horn, log-periodic
pyramid, cavity backed Archimedean spiral, tapered slot areal and bicon antennas) are taken and
analyzed and compared along with time domain analysis and modelling of channel in multi path
propagation. In geometrical approach, different possible geometry is taken and deigned for different
application in ultra wide band range for different range of frequency of operation, different band width,
patterns with multiple notch.
Drive test Analysis for a 3rd Generation of GSM System and its EMF Survey
A Comparative Design and Analysis of Broadband Rectenna application to wireless Energy Generation
Design & Performance comparison of 8*8 Multiplier circuit using Modified Gate Diffusion Input Adder cell
Application of Integrated Single Pole Auto Tripping and Reclosing System in IEEE Benchmark Two-Area Power System
This paper focuses on the protection of three phase high voltage two area power system by using a new
advanced integrated SPAT and SPAR method. It overcomes the drawbacks of conventional auto tripping
and reclosing system. This paper aims in introducing a reliable and more stable two area power system.
The performance of an isolated generating station connected to the load center improves through single,
double and three phase transmission lines due to the planned integrated SPAR network. The
interconnected system uses the same measuring functions for both fault tripping zone and fault phase
identification. The proposed method is verified using IEEE kundur’s two-area system. The proposed
method is simulated in MATLAB/SIMULINK environment
Design and Implementation of Surface Cleaning Robot
Robotics application in surface cleaning are getting more attention now a days. This paper presents controller design and implementation of a surface cleaning robot. The robot presented is designed on the RF principle. The design consists of an 8051 microcontroller which is the main building block of the design. The control system developed in this work able to control the movement of the robot in forward, backward and as well as turn. The proposed design is simulated in proteus software and a prototype is developed to demonstrate the working of the model.
Free and Open Source Software Simulation Techniques for Analog & Digital Modulation Schemes for Teaching Undergraduate Students
Simulating mathematical topics are an enticing way of illustrating scientific concepts taught during lectures. Online teaching of mathematics concentrated designing-based courses to undergraduates represents an incredible test to instructors. This paper provides a mode to impart digital modulation concepts as well as analog modulation concepts, which eases the need for a strong mathematical foundation to students. The free and open source software (FOSS) such as Octave used to simulate and learn through the visuals of analog and digital modulation techniques without usage of mathematical formulations.
PWM Bridgeless CUK Converter using Soft Switching Technique
The single phase high efficient ac to dc PWM bridgeless CUK converter using soft switching method is being presented here. The proposed converter offers low conduction switching method is being presented here. loss and less input current harmonics because of the absence bridge input diode and also uses two semiconductor switches are available in the current flowing in the path during each of the switching cycle unlike other types of conventional CUK converters. The efficiency can be improved of the proposed converter which uses soft switching technique by using the help of auxiliary circuit. The output voltage can be regulated by using output voltage regulating control which improves the efficiency. As the input current harmonics is less so the power factor is almost equal to one. The circuit arrangement, performance, design principle and simulated output results are introduced here.
Design and Implementation of STG Based Sequential Multiplier
Combinational multipliers operate fast, but require a significant amount of silicon area. As area is an important consideration, it can be reduced at the expense of performance by scheduling the sub-operations of the multiplier to execute in successive clock cycles. Sequential multipliers are compact, require fewer adders, and are amenable to pipelining. The area required by combinational multipliers grows geometrically with the word length, but the area of a sequential multiplier does not grow significantly with word length and that the number of clock cycles required completing a multiplication also grows in a linear manner, rather than exponentially, with the word length. The paper presents design and synthesis of sequential multiplier based on state transition graph (STG) controller. The proposed multiplier is designed and synthesized using Verilog programming in Xilinx ISE. Simulation results and RTL diagrams are presented to validate the sequential multiplier operations.
Design and Synthesis of Datapath Controller
The processors are basically categorized into two components such as data path which contains all the required hardware to perform different operations and the second one is controller unit which determines the datapath operations. The paper presents the design and synthesis of a data path controller using different approaches. The work is demonstrated through design 4 bit counter consisting of datapath and control unit. The presented work is simulated using Xilinx ISE Design suite using Verilog programming. Top module and RTL of the system is obtained through synthesis process. Testbench code has been implemented to the design for validation of the system.
Design and Implementation of VGA Controller Using FPGA
The processors are basically categorized into two components such as data path which contains all the required hardware to perform different operations and the second one is controller unit which determines the datapath operations. The paper presents the design and synthesis of a data path controller using different approaches. The work is demonstrated through design 4 bit counter consisting of datapath and control unit. The presented work is simulated using Xilinx ISE Design suite using Verilog programming. Top module and RTL of the system is obtained through synthesis process. Testbench code has been implemented to the design for validation of the system.platform using Verilog programming. In this work VGA timing is generated whose position and even size can be changed. The Code is synthesized and netlist is generated to obtain the bit stream for FPGA implementation. VGA video signal contains 5 active signals. H_sync, V_sync, R, G, B. By changing the three RGB signals all other colors are produced. RTL of the design is obtained and simulation results are presented to validate the design.
Color Objects Detection in Real -Time with Raspberry Pi and Image Processing
DMTL Design and Antenna Fundamentals(BOOK)
Introduction and current uses of MEMS
RF MEMS Transmission Line Model
DMTL Design
DMTL Simulation and Results
L and C Parameter Extraction
A Review on State- of -Art CMOS Circuits and Nano Accelerator
Book Chapter published under Book Titled "Project Management and Smart Electrical System"
Design and Investigation of Hexagonal Shaped Wearable Antenna for Body Centric Wireless Communication
Abstract—This paper introduces a hexagonal shaped wearable antenna. The prototype modelled in this paper will be used for body Centric wireless Communications working in the band of 2.45 GHz-5.8 GHz Industrial, Scientific and Medical band. In addition, a satisfactory gain characteristic has been attained.
Different Fractal Antenna Structure Analysis using ANN
Abstract: In this paper various geometrical shapes, derived from fractal mathematics have been simulated for obtaining its multiband or wideband features. Design of fractal antennas involves a lot of calculations. In order to ease the calculation, the Artificial Neural Network (ANN) is implemented. The results obtained from ANN are in accordance with the measured results.
Superposition Modulation and its Power Distribution Method
Superposition Modulation (SM) is a novel mapping technique that uses linear superposition to load binary digits onto finite number of alphabet symbols that are suitable for signal transmission. SM performs superior compared to bit-interleaved coded modulation with PSK or QAM. It is an alternative to signal shaping for approaching the channel capacity in the high SNR case. SM has been examined with different power allocation schemes namely Equal Power Allocation (EPA), Unequal Power Allocation (UPA) and Grouped Power Allocation (GPA) for capacity achievement.
Superposition Modulation (SM) is a novel mapping technique that uses linear superposition to load binary digits onto finite number of alphabet symbols that are suitable for signal transmission. SM performs superior compared to bit-interleaved coded modulation with PSK or QAM. It is an alternative to signal shaping for approaching the channel capacity in the high SNR case. SM has been examined with different power allocation schemes namely Equal Power Allocation (EPA), Unequal Power Allocation (UPA) and Grouped Power Allocation (GPA) for capacity achievement.